The present invention relates to a phase synchronization system for aligning the phases of basic operation clock signals of central processors in a system including a plurality of central processors activated by those basic operation clock signals.
In a conventional system such as a multiprocessor system, basic operation clock signals for activating respective central processors are generally produced by a basic operation clock generator disposed in common to respective central processors and supplied to respective central processors to synchronize the operation of central processors with each other. FIG. 4 shows an example of a configuration of a clock signal supply circuit. On the basis of a system clock supplied from an oscillator 1, a basic operation clock generator 20 produces basic operation clock signals for activating respective central processors 30 and supplies them to respective central processors 30.
Such a configuration is adopted to reduce the size of the basic operation clock generator which is a common part. With the progress of the integrated circuit technology, however, the factors defining the physical dimensions tend to heavily depend on not only the logic size but also the number of input and output terminals. Since the basic operation clock signals must be distributed to respective central processors in the configuration exemplified in FIG. 4, therefore, the number of output terminals of the basic operation clock generator is defined by the number of central processors 30 supplied with the basic operation clock signals. The limit in physical size reduction of the basic operation clock generator 20 is thus defined. As a result, the size reduction of the system is hampered and its cost might be increased.
In one countermeasure to such drawbacks, basic operation clock generators are disposed for each central processor as shown in FIG. 5, for example. In a central processing unit 2 of FIG. 5, for example, a basic operation clock generator 21 produces a basic operation clock signal for a central processor 22 on the basis of the system clock signal supplied from an oscillator 1 and supplies the basic operation clock signal to the central processor 22. Similar operation is conducted in other central processing units.
In the configuration as shown in FIG. 5, the basic operation clock generator needs to supply the basic operation clock signal only to the central processor within its own central processing unit, optimization in the central processing unit being enabled. Further, the reduction in the number of input and output terminals of the basic operation clock generator facilitates the size reduction of the system and the use of VLSI's in the system. In addition, this configuration is advantageously employed when a multiprocessor system is to be arranged by building up a plurality of single processors each including one central processing unit or by increasing the number of single multiprocessor systems. It is thus possible to obtain a wide variety of computer line ups by using an identical hardware configuration.
When the configuration as shown in FIG. 5 is employed, however, phase synchronization between the basic operation clock signals for attaining synchronization between the central processors poses a problem.
A method for aligning phases of basic operation clock signals of a plurality of apparatuses included in a system and activated by those basic operation clock signals having identical repetition periods as shown in FIG. 5 is described in Japanese Patent Unexamined Publication No. 123911/84, for example.
In accordance with this technique, microprocessors respectively placed with respect to two apparatuses divide the frequency of clock signal supplied from a clock source and supply bus clock signals to the associated apparatuses. In order to synchronize bus clock signals supplied to respective apparatuses, both clock signals are supplied to an AND circuit. As long as a timing error signal is sent out from the AND circuit, one of the microprocessors is not supplied with clock signals so that one of the microprocessors may not apply frequency division to clock signals supplied from the clock source. Thereby, the bus clock signal of one of the microprocessors is delayed and the mutual phase relations are successively shifted. Finally, the phases of both bus clock signals are aligned with each other. When this method is used, however, the phase difference of bus clock signals between apparatuses must be detected. Therefore, the configuration of the AND circuit varies according to the number of apparatuses forming the system. And, the AND circuit tends to become complicated as the number of apparatuses is increased. Further, synchronization tends to be time-consuming when the bus clock signals are generated at low speed or sporadically, because the phase relations are successively shifted to attain synchronization.